Method and apparatus for acquiring a synchronization signal

ABSTRACT

A method and system for acquiring a time division multiplexed synchronization signal in a satellite communication system is provided. The signal is provided as a series of frames with beacon signals time division multiplexed into at least one time slot of each frame. The beacon signal in each frame comprises a unique word sequence, which is the same in each frame, and a portion of a PN sequence. The entire PN sequence is distributed into a plurality of frames forming a superframe. Initially, the power level of the incoming signal is determined by locating the maximum power received in half time slot intervals. Next a series of frames are correlated against the expected unique word, each at one of a plurality of possible frequencies. The frequency generating the maximum correlation with the unique word is selected. The frequency is fine tuned by comparing the actual arrival time of the unique word in each frame with the estimated arrival time based on the current frequency, and adjusting the frequency accordingly. Also, the start of the superframe is located by correlating the PN sequence portion of each beacon signal against a known PN sequence until a match is found. Once the frequency offset is reduced below a threshold value, and the start of the PN sequence of the incoming signal is located, acquisition is completed.

[0001] This application claims the benefit of priority under 35 U.S.C.§119(e) to U.S. Patent Application Serial No. 60/214,163 filed Jun. 26,2000.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a method and system forsynchronizing downlink and uplink signals between a satellite andsatellite terminals in a satellite communication system. Moreparticularly, the present invention relates to a method and system forsynchronizing downlink and uplink signals between a satellite andsatellite terminals in a satellite communication system using adiscontinuous synchronization signal embedded within frames of thedownlink signal.

[0004] 2. Description of the Related Art

[0005] Society has an ever increasing appetite for the exchange ofinformation. A number of communication systems exist which attempt tosatisfy society's communications needs. A useful communication systemshould be reliable, inexpensive and available to a wide percentage ofthe population, even in geographically remote areas. Existingcommunication systems each have disadvantages. For example, digitalsubscriber line (xDSL) services have been proposed to accommodate thetransport of digitized voice and data on analog telephone lines.However, difficulties have been experienced with insuring that xDSLservices consistently deliver the bandwidth that is requested by users.

[0006] In addition, large populations exist that do not have access toplain old telephone service (POTS). Furthermore, even where POTS isavailable, xDSL services may not be available because of the distancebetween a consumer and a central office, or because of problems withnoise on the analog telephone line. Some cable companies offer highspeed internet services over existing cable networks. However, access tocable internet service, like DSL, is limited to geographic regions wherethe infrastructure exists. Furthermore, it would be extremely expensiveto build the infrastructure for telephone or cable service in suchgeographically remote areas.

[0007] Other examples of communication systems include wireless networksto provide for the transmission of packetized data over cellular voicenetworks, personal communication systems (PCS), and point-to-multipointsystems for broad-band wireless network access. These systems aredisadvantageous in that they limit users delivery options. For example,cellular voice networks are limited to voice communications and personalcommunication systems provide access to either very limited informationor provide internet access at relatively slow data rates compared toeven dial-up connections. Furthermore, cellular and PCS systems arestill geographically limited to locations where the cellularinfrastructure exists.

[0008] Satellite communication systems are advantageous because they canserve an extremely wide geographic region. For example, a singlegeosynchronous satellite may service the entire North Americancontinent. Very small aperture terminal (VSAT) satellite networksprovide business enterprises and other organizations with local areanetwork (LAN) internetworking, batch and interactive transmissionservice, interactive voice, broadcast data and voice communications,multimedia image transfer service, and other services, between a numberof sites equipped with VSATs and a site designated as theirheadquarters. Some existing VSAT satellite networks, however, aredisadvantageous in that they typically use large antennas, requiredouble satellite hops through a central hub for VSAT to VSAT datatransfers, and transmit and receive at relatively low data rates. Othersatellite systems provide only push internet service to consumers (i.e.access to selected information available via internet) and not fullaccess to all internet information and full connectivity.

[0009] There is therefore a need for a satellite communication systemthat overcomes the above-listed disadvantages. Such a system shouldprovide broadband multimedia services to an individual or entity withinthe geographic area covered by the satellite. In the case of ageosynchronic satellite, customers in the northern hemisphere shouldrequire only a clear view of the southern sky and a satellite terminalcapable of receiving from and transmitting to the satellite.

[0010] Two very important considerations in a two-way satellitecommunication system will be the system's capacity and the cost of thesatellite terminals. The capacity of the system is determined by thefrequency band allocated to the system. For Ka band Fixed SatelliteServices, a contiguous spectrum of 500 MHz is typically allocated forthe downlink as well as the uplink. The capacity of the system isincreased by dividing the coverage area into geographically distinctuplink and downlink cells. Multiple modulators and beam shaping isutilized on the satellite to limit the coverage of each beam to aparticular cell or group of cells. In this manner, the allocatedspectrum may be reused in geographically distinct areas. However, usingmultiple modulators increases the complexity of a satellite. Therefore,there is a need to reduce the complexity of the satellite wherepossible.

[0011] In addition, the cost of satellite terminals (ST) should be keptto a minimum. Because many STs will be present within each uplink anddownlink cell, each uplink cell is typically assigned to a particularsub-band of the allocated spectrum, and each ST within the uplink cellis typically assigned to a particular time slot. Thus, it is critical tothe functioning of the system for the STs to be synchronized in bothtiming and frequency with the satellite. Traditional satellite systemsincorporate a beacon signal on a separate carrier frequency in order tosynchronize the ST with the satellite. However, providing a beaconsignal on a separate carrier requires an additional modulator on thesatellite and additional hardware for demodulating at the ST. This addsunwanted cost and complexity to the system. Therefore, there is a needto provide a means for synchronizing STs with the satellite to a highdegree of accuracy while at the same time reducing the cost andcomplexity of the STs and the satellite.

SUMMARY OF THE INVENTION

[0012] It is an object of the present invention to provide a satellitecommunication system including at least one satellite that transmitssignals to and receives signals from a plurality of satellite terminals.The satellite terminals will be synchronized with the satellite. It isanother object of the invention to allow the satellite to have reducedcomplexity by reducing the number of modulators. It is a further objectof the invention to provide satellite terminals with a means foracquiring a TDM synchronization signal.

[0013] The above listed objects are accomplished by providing a systemand method of time division multiplexing a beacon signal into downlinkframes of a communication signal on a single carrier. A system andmethod in accordance with one embodiment of the invention provides asynchronization signal to a terminal which is adapted for use in acommunication network. A signal is transmitted to a terminal whichincludes a plurality of frames, with each frame including at least onetime slot. At least one time slot in each of the frames (or in periodicframes) includes a respective portion of a synchronization signal, thesynchronization signal including data which is adapted for use by theterminal to control transmission timing of the terminal.

[0014] In accordance with another aspect of the invention, a system andmethod of acquiring a satellite signal at a satellite terminal isprovided. The system and method includes a transmitter for transmittinga signal, comprising a plurality of frames time divided into a pluralityof time slots, with at least one time slot in each frame (or in periodicframes) comprising a portion of a beacon signal, to a satelliteterminal. The signal is received and sampled at the satellite terminalin a plurality of consecutive time windows, with each time window beingno longer then one half of the time slot. The power received from thesignal in each time window is measured. The time window in which themaximum power was received from the signal is identified and anautomatic gain control circuit is set based on the power measured in themaximum power time window.

[0015] Another embodiment of the invention provides a system and methodof acquiring a signal being transmitted on at least one of a pluralityof carrier frequencies. The system and method includes a receiver forreceiving a signal at a satellite terminal, with the signal comprising aplurality of frames, with a portion of each frame or periodic framescomprising a unique word pattern. The signal is tested at each of saidplurality of carrier frequencies for the duration of at least one frame(or period of frames) for the presence of the unique word pattern. Amaximum correlation value is obtained for each of said possible carrierfrequencies, and then an actual frequency value is determined from thecarrier frequency associated with the highest maximum correlation value.

[0016] Still another embodiment of the present invention provides asystem and method for providing a synchronization signal to a terminaladapted for use in a satellite communication system. The system andmethod generates a plurality of unique phase signals, and transmits asynchronization signal to a satellite terminal such that thesynchronization signal comprises a plurality of frames, with a portionof each frame (or each periodic frame) comprising a unique one of therespective unique phase signals. Also, the synchronization signal cancomprise a plurality of superframes with each superframe comprising aplurality of frames such that the order of the unique phase signals ineach frame (or periodic frame) repeats in each superframe. The number offrames per superframe can be equal to the number of unique phasesignals.

[0017] Another embodiment of the present invention provides a system andmethod of confirming acquisition of a synchronization signal by aterminal adapted for use in a satellite communication system. The systemand method employs a receiver for receiving a signal comprising aplurality of frames, with each frame (or a periodic frame) containing atiming signal in substantially the same temporal location relative tostart of the frame. The receiver is capable of detecting the presence ofthe timing signal in the first frame, calculating an expecting arrivaltime of the timing signal in the second frame, sampling a portion of thesecond frame corresponding to the expected arrival time of the portion,and testing for the presence for the timing signal within the portion ofthe second frame.

[0018] A further embodiment of the invention provides a system andmethod for tracking frequency shifts in a satellite transmission. Thesystem and method employs a transmitter for transmitting a signal to asatellite terminal with the signal being time divided into a pluralityof frames, and each frame being further time divided into a plurality oftime slots. At least one of the time slots in each frame (or in periodicframes) includes a unique word pattern. The terminal estimates theamount of time between the detection of subsequent unique word patterns,and then calculates the actual time between detection of a first uniqueword pattern in a first frame and detection of a second unique wordpattern in a second frame. The local clock frequency of the terminal isthen adjusted based on the difference between the estimated amount oftime and the actual amount of time between detection of the first uniqueword pattern and the second unique word pattern.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The various aspects, advantages and novel features of the presentinvention will be more literally comprehended from the followingdetailed description when read in conjunction with the appendeddrawings, in which:

[0020]FIG. 1 illustrates an example of a satellite communication systemwhich employs an embodiment of the present invention for acquiring andtracking communication signals;

[0021]FIG. 2 is a block diagram illustrating the exemplary components ofa satellite terminal employed in the system shown in FIG. 1 inaccordance with an embodiment of the present invention;

[0022]FIG. 3 is a block diagram illustrating further details of anexample of the acquisition block of a satellite terminal shown in FIG. 2in accordance with an embodiment of the present invention;

[0023]FIG. 4 is a block diagram illustrating further details of anexample of the start-up block within the acquisition block shown in FIG.3 in accordance with an embodiment of the present invention;

[0024]FIG. 5 is a block diagram illustrating further details of anexample of the acquisition control block within the start-up block shownin FIG. 4;

[0025]FIG. 6 illustrates further details of an example of the trackingblock included in the satellite terminal components shown in FIG. 2;

[0026]FIG. 7 illustrates further details of an example of thediscriminate function block employed in the tracking block shown in FIG.6;

[0027]FIG. 8 illustrates an example of the output of the discriminatefunction block shown in FIG. 7 for different normalized timing errors;

[0028]FIG. 9 is a block diagram showing further details of an example ofthe signal power estimation block of the tracking block shown in FIG. 6;

[0029]FIG. 10 is a block diagram showing further details of an exampleof the frequency control block included in the components shown in FIG.2;

[0030]FIG. 11 is a block diagram showing further details of an exampleof the AGC block included in the components shown in FIG. 2;

[0031]FIG. 12 is a block diagram illustrating further details of anexample of the DRO Frequency Offset Estimator and Lock Detector blockincluded in the components shown in FIG. 2;

[0032]FIG. 13 illustrates an example of one superframe of the downlinksignal received by a satellite terminal in the system shown in FIG. 1;

[0033]FIG. 14 illustrates an example of the beacon portion of thedownlink signal;

[0034]FIG. 15 is a flowchart illustrating an example of the operationsperformed by the components shown in FIG. 2 for demodulation, and signalacquisition and tracking of a beacon signal in accordance with anembodiment of the present invention;

[0035]FIG. 16 is a flowchart illustrating an example of operationsperformed by the components shown in FIG. 2 during an acquisition mode;

[0036]FIG. 17 is a flowchart illustrating in greater detail, an exampleof the frequency acquisition and UW lock confirmation steps of theflowchart shown in FIG. 16;

[0037]FIG. 18 is a flowchart illustrating in greater detail an exampleof the frequency acquisition operations in the flowchart of FIG. 17;

[0038]FIG. 19 is a flowchart illustrating an example of operationsperformed by the threshold control block shown in FIG. 5;

[0039]FIG. 20 is a flowchart illustrating an example of the operationsperformed by the false UW lock control block shown in FIG. 5;

[0040]FIG. 21 is a flowchart illustrating an example of the operationsperformed by the search window control block shown in FIG. 5;

[0041]FIG. 22 is a flowchart illustrating in further detail an exampleof operations performed by the coarse VCO frequency pull-up step of theflowchart in FIG. 16;

[0042]FIG. 23 is a further illustration of an example of the coarse VCOfrequency pull-up computations performed in the corresponding step inthe flowchart of FIG. 22;

[0043]FIG. 24 is a timeline illustrating an example of how the uniqueword delta (D_(UW)) is calculated by the coarse VCO frequency pull-upblock shown in FIG. 3;

[0044]FIG. 25 is a flowchart illustrating an example of operationsperformed by the PN Sequence Generator block included among thecomponents shown in FIG. 2;

[0045]FIG. 26 is a flowchart illustrating an example of operationsperformed by the DRO Frequency Offset Estimator and Lock Detector blockincluded among the components shown in FIG. 2; and

[0046]FIG. 27 is a flowchart illustrating an example of operationsperformed by the components shown in FIG. 2 during a tracking mode.

[0047] Throughout the drawing figures, the same reference numerals willbe understood or refer to the same parts and components.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0048] A satellite communications system 100 employing an embodiment ofthe present invention is shown in FIG. 1. The system 100 includes atleast one satellite 102, such as a geosynchronous earth orbit (GEO)satellite, that transmits downlink signals 104 to a plurality ofsatellite terminals (ST's) 106. The STs 106 in turn transmit uplinksignals 108 to the satellite 102. The uplink signals 108 from themultiple STs 106 are transmitted over the same carrier signal in a timedivision multiplexed manner in order not to interfere with one another.Therefore, in order for the satellite communications system to functionproperly, the STs 106 must be synchronized to the satellite and to eachother.

[0049] In accordance with an embodiment of the present invention,synchronization can be accomplished through the use of a beacon signalincorporated into the downlink signal 104. The downlink signal is timedivided into frames, preferably 3 msec frames, with each frame furtherdivided into time slots. At least one time slot, preferably the firsttime slot, in each frame contains the beacon signal, which will bedescribed in further detail below. The STs 106 receive the beaconsignal, and in combination with satellite ephemeris information are ableto coordinate their respective transmissions of their respective uplinksignals so that they arrive at the satellite 102 in their respectiveassigned time slots.

[0050] Each ST 106 contains a beacon demodulator 112 as shown in FIG. 2.The ST 106 receives the downlink signal 104 and delivers it to beacondemodulator 112 at an IF/baseband down-converter 114. An automatic gaincontrol circuit 116 (AGC) controls the gain applied to the signal at theIF/baseband down-converter 114. The signal 104 is then filtered in dualanti-aliasing filter 118 and passed to dual A/D converter 120. The A/Dconverter 120 converts the analog wave form 104 into digital samples,such as for example six bit samples, at a rate determined by a 10 MHzVCO 122. Specifically, the 10 MHz clock signal produced by VCO 122 isfirst increased to 133.33 MHz by a 40/3 frequency multiplier 124, andthen up to the 800 MHz sampling rate by a ×6 frequency multiplier 126.The 800 MHz clock received by A/D converter 120 causes the converter 120to produce six samples per QPSK symbol (the satellite 102 transmits133.33 million QPSK symbols per second, thus the 800 MHz clock producessix samples per QPSK symbol received) of the received signal 104.

[0051] As further shown, the output of dual A/D converter 120 iscombined with the output of NCO and Control Logic block 128 atmultiplier 130. The output of multiplier 130 is received by a modeswitch 132 and by a DRO Frequency Offset Estimator and Lock Detector134, the details of which are described below. The samples received atthe mode switch 132 from the multiplier 130 are sent to either anacquisition block 136 or a tracking block 138 based on a control signalreceived at mode switch 132 from mode selection control block 140. Theoutput of the acquisition block 136 or the tracking block 138 is sent toa second mode switch 142 which in turn passes the output to a digital toanalog converter 144. The output of digital to analog converter 144adjusts the frequency of the VCO 122.

[0052] The beacon demodulator 112 further includes a PN sequencegenerator 146 which provides an on-time PN sequence signal to DROFrequency Offset Estimator and Lock Detector 134, and both early andlate PN sequence signals to the tracking block 138. The PN sequencegenerator block 146 is clocked by the output of the 40/3 block 124, onceper received QPSK symbol. Furthermore, the PN sequence generator block146 receives a control signal from the mode selection control block 140.

[0053] The beacon demodulator 112 further includes a frequency controlblock 148. The frequency control block 148 receives control signals fromthe DRO frequency offset estimator, and lock detector 134 and from theacquisition block 136. The frequency control 148 also provides an outputwhich is received by the NCO and control logic block 128 and used toadjust the frequency at the NCO and control logic block 128.

[0054] The mode selection control block 140 provides a reset signal tothe acquisition block 136, the tracking block 138 and frequency controlblock 148. The mode selection control block also receives a controlsignal from DRO frequency offset estimator, and lock detector 134.Finally, AGC 116 receives a control signal from either the acquisitionblock 136 or the tracking block 138 depending on the status of the modeselection control block 140 and mode switch 132.

[0055] Acquisition block 136 is shown in greater detail in FIG. 3. Inaccordance with this embodiment, acquisition block 136 contains start-upblock 150 and coarse VCO frequency pull-up block 152. Samples of theinput signal are received and processed by start-up block 150. A resetsignal is also received by start-up block 150 and coarse VCO pull-upblock 152. Start-up block 150 provides a flag acquisition controlsignal, Flag_Aq, to coarse VCO pull-up block 152. A unique word deltasignal (D_(UW)) is provided by the coarse VCO frequency pull-up block152 to the start-up block 150. The acquisition block 136 has a number ofoutput signals including a reset signal, an NCO frequency offset signal(f_(NCO1)) which is provided to the frequency control block 148, anacquisition flag (Flag_Aq) which is also, as shown, available to aninstaller as a beacon acquired signal (BAS), a PN timing signal (t_(PN))which is provided to the PN generator block 146, a c_max value which isavailable to the installer as a beacon strength indicator (BSI), asignal power value (S_(P))which is provided to the AGC block 116, a VCOfrequency offset signal (f_(VCO))which is provided to the VCO, andfinally a pull-up flag (Flag_pull) which is provided to the modeselection control block 140.

[0056] Start-up block 150 is shown in further detail in FIG. 4. Thestart-up block 150 is comprised of a decimator block 154, a unique wordcorrelator block 156, a time estimation block 158, an acquisitioncontrol block 160, a frequency estimation block 162 and a signal powerestimation block 164. The decimator block 154 receives input samples andprovides a decimated sample sequence to unique word correlator block 156and signal power estimation block 164. The unique correlator block 156receives the decimated set of samples and correlates them against aknown unique word pattern. The unique word correlator block 156 thencalculates a series of c_num and c_den values based on the correlationas will be described in more detail below. C_num and c_den are providedto the time estimation block 158.

[0057] The time estimation block 158 calculates a unique word timingsignal and a PN timing signal based on the received c_num and c_denvalues. The time estimation block 158 further calculates a c_max valueand a corr_max value. C_max is provided to the acquisition control block160 and as an output of the start-up block 150. The corr_max value isprovided to the signal power estimation block 164. The acquisitioncontrol block 160 provides a search flag (Flag_Search) for the uniqueword correlator block 156. The acquisition control block 160 furtherprovides the acquisition flag (Flag_Aq) both as an output of thestart-up block 150 and as an input to the signal power estimation block164, and further provides a frequency control signal (Fr_Control) aswell as c_max_buf and n_max values to the frequency estimation block162. Also, the acquisition control block 160 generates a reset signalbased on the status of the acquisition process. Finally, the frequencyestimation block 162 generates NCO frequency offset signals (f_(NCO1))which are provided as an output of the start-up block 150.

[0058] Acquisition control block 160 is shown in further detail in FIG.5. The acquisition control block 160 has a frequency search controlblock 166, an acquisition control state machine 168 and a time searchcontrol block 170. The time search control block 170 is furthercomprised of a threshold control block 172, a search window controlblock 174 and false UW lock control block 176. Acquisition control block160 has three inputs. The reset signal from mode selection control block142 is received by an OR gate 178. Acquisition control state machine 168generates a second reset signal which is also received at OR gate 178.The output of OR gate 178 is a reset signal received by the frequencysearch control block 166, the false UW lock control block 176 and thesearch window control block 174, as well as being passed on to thefrequency control block 148. The c_max value from time estimation block158 is received by the frequency search control block 166 and thethreshold control block 172. The unique word delta value (D_(UW)) fromcoarse VCO pull-up block 152 is received by the search window controlblock 174. Frequency search control block 166 produces three outputs.The value of c_max_buf and the control signal Fr_Control are deliveredto the frequency estimation block 162. Control signal Fr_Search is sentto acquisition control sate machine 168. The functionality of thefrequency search control block 166 will be described in greater detailbelow.

[0059] Acquisition control state machine 168 has four inputs and threeoutputs. The inputs are Fr_Search from frequency search control block166 Th_Fail from threshold control block 172, a search flag(Flag_Search) from search window control block 174 and a false lockcontrol signal (false_lock) from OR gate 180. The outputs of acquisitioncontrol state machine 168 are a frequency acquisition flag (Flag_Fr_Aq)which is delivered to time search control block 170 and acquisition flag(Flag_Aq) which is delivered to coarse VCO pull-up block 152, a resetsignal is also generated and delivered to OR gate 178. The functionalityof acquisition control state machine 168 is further described in thefollowing state transition Table 1: TABLE 1 State Transition TablePresent Inputs Next Outputs State Fr_Search False_lock Flag_searchTh_fail State Flag_Fr_Aq Flag_Aq Reset 0 0 × × × 0 0 0 0 0 1 × × × 1 1 00 1 × 0 0 0 1 1 0 0 1 × 0 1 0 1 1 1 0 1 × × × 1 0 0 0 1 1 × 1 × × 0 0 01

[0060]FIG. 6 shows tracking block 138 from FIG. 2 in greater detail. Atracking block 138 comprises a signal power estimation functions block182, a tracking control block 184, a discriminate function block 186 anda loop filter block 188. The loop filter block 188 is further comprisedof simple gain function 190 and third order loop filter function 192.The input samples are received at the signal power estimation functionsblock 182 and at the discriminate function block 186. The reset signalis received at tracking control block 184. The signal power estimationfunctions block 182 generates a signal power value (S_(P)), signal whichis sent to AGC block 112 and a c_max value which is available to theinstaller as the beacon strength indicator (BSI). In addition toreceiving samples, the discriminate function 186 receives early and lateversions of the PN sequence from the PN sequency generator 146. Thediscriminate function compares the incoming samples but both the earlyand late versions of the PN signal and generates a discriminate functionvalue which is used by both simple gain block 190 and third order loopfilter block 192. The functionality of the discriminate function block186 will be described in greater detail below. Simple gain block 190 orthe third order loop filter block 192 are alternatively enabled by afilter flag signal (Flag_filter) supplied by tracking control block 184.The output of loop filter block 188 is a VCO frequency offset value(f_(VCO)) that is sent to mode switch 42 and from there on to the VCO toadjust the VCO frequency.

[0061]FIG. 7 shows discriminate function block 186 in greater detail.Input samples are received at discriminate function block 186 anddelivered to multipliers 194 and 196. The multipliers 194, 196 receiveearly and late versions of the PN sequence from PN sequence generator146 respectively. Multiplier 194 multiplies each sample of the incomingstream by a sample of the late PN sequence and multiplier 196 multiplieseach sample of the incoming signal by one sample of the early PNsequence. The resulting multiplied early samples are then summed insummer block 198 while the multiplied samples of the late PN sequenceare summed in summer block 200. Early and late summation values are thensent to absolute magnitude function blocks 202 and 204. The absolutefunction blocks square the I and Q portions of the received signal andproduce absolute magnitude values (|M|²). The absolute magnitudes of theearly and late correlations are then compared at comparator 206. Theoutput of comparator 206 is a discriminate function value which isprovided to the loop filter 188.

[0062]FIG. 8 shows an example of the output of the discriminatorfunction block 186 for different normalized timing errors. Positivevalues of the discriminator output indicate that the incoming PNsequencing early on negative values indicate that the incoming PNsequence late. As shown, the discriminator output has a linear responsebetween the minimum value at one-half of a symbol late and the maximumvalue at one half of a symbol early. At ranges between one-and-a-halfsymbols later and one-and-a-half symbols early, a discriminate output ofzero indicates that the incoming PN sequence is exactly on time. Thisoutput is in turn used by loop filter 188, to generate a VCO frequencyoffset (f_(VCO)) to be used to adjust the VCO frequency.

[0063] Signal power estimation functions block 182 is shown in greaterdetail in FIG. 9. Input samples are received by a decimator block 208.The decimator block decimates the sample sequence and produces adecimated sample sequence (d[k]) which is passed on to the on-time UWcorrelator block 210. The on-time UW correlator block 210 correlates thedecimated sample sequence against the known unique word sequence andproduces two values. The first value, c_max, is available to aninstaller as the beacon strength indicator. The second value, corr_max,is sent to a signal power estimation block 212. The signal powerestimation block 212 generates a signal power value (S_(P)) which issent to the AGC block 112 to determine the gain to be applied to theincoming wave form.

[0064] Frequency control block 148 of FIG. 2 is shown in greater detailin FIG. 10. The frequency control block 148 receives two NCO frequencyoffset signals, f_(NCO1) and f_(NCO2). Frequency offset signal f_(NCO1)is received from the acquisition block 136. Frequency offset signalf_(NCO2) is received from the DRO frequency offset estimator, and lockdetector block 134. Both frequency offset signals are received atfrequency offset selector block 214 and selected based on the value ofthe acquisition flag, Flag_Aq. The selected frequency offset value ispassed on to a summer block 216. The summer block adds the frequencyoffset value to the current beacon frequency value (F_(BEACON)) togenerate a new beacon frequency value. The beacon frequency value is inturn passed on to the NCO to control the frequency of the NCO. Thesummer block also receives the reset signal which resets the NCOfrequency value to zero.

[0065] The AGC block 112 of FIG. 2 is shown in greater detail in FIG.11. The signal power value (S_(P)) is received by AGC block 112 andmultiplied by the factor K_(d) in multiplier block 218. The output ofmultiplier block K_(d) 218 is sent to a comparator 220. A referencepower signal is square-rooted at square-root function block 222 and thencompared against the output of multiplier block K_(d).218 at comparator220. A signal representing the difference between the two inputs of thecomparator 220 is output to a function block 224. The output of thefunction block 224 is the value of the gain to be applied to theincoming wave form. This conditions the incoming wave form signal sothat the data converter 120 can properly resolve the incoming wave forminto digital samples. Without the gain value the wave form inputted tothe D/A convertor 120 might be out of the range of the D/A convertor 120causing the output of the A/D converter to be either saturated or allzeroes.

[0066] The DRO frequency offset estimator and lock detector 134 of FIG.2 is shown in greater detail in FIG. 12. In the DRO frequency offsetestimator and lock detector 134 the received input samples aremultiplied at multiplier 226 with samples representing an on-time PNsequence received from PN sequence generator 146. A series of samplesrepresenting the product of the on-time PN sequence with the receivedsamples is output from multiplier 226 and sent to decimator 228. Thedecimator 228 decimates the number of samples in the received productsequence and outputs a decimated sequence (d[n]) to a 128 point FFTblock 230. The output of the 128 FFT block 130 is 128 indexed values(y[i]) representing the magnitudes of 128 frequency components generatedfrom the decimated input samples. The 128 frequency component magnitudevalues are generated in each of the 128 frequency bins of the 128 FFTblock 130.

[0067] The lock detector 232 receives the 128 frequency componentmagnitude values and generates a lock flag (flag_lock ) and a maximumindex value, i_max. The maximum index is the index number of the maximumvalue frequency component from FFT block 130. The lock flag indicateswhether or not the incoming signal is locked with the on-time PN signal.The lock flag is then sent to both a frequency estimator 234 and modeselection control block 140. The value i_max is also sent to thefrequency estimator 234. The frequency estimator block 234 receives themaximum index value, i_max and the lock flag and determines an NCOfrequency offset value to be sent to the frequency control block 148.The NCO frequency offset value, f_(NCO2) will be used to adjust thefrequency of the NCO in the NCO and control logic block 128.

[0068] Downlink Signal

[0069] The features of the downlink signal 104 that is received by thebeacon demodulator 112 will now be described in detail. The downlinksignal 104 is unique in that the beacon information and the data areboth incorporated into the same carrier signal. An example of the formatof the downlink signal 104 is illustrated in FIG. 13. The downlinksignal is transmitted as a series of 3 msec downlink frames 236. Thedownlink frames are divided into time division multiplexed (TDM) timeslots. The first time slot in each frame is a TDM beacon slot 238. Thebeacon slot 238 in each frame contains both a unique word sequence and aportion of the PN sequence. A series of 256 downlink frames forms a 768msec superframe 240.

[0070]FIG. 14 shows the beacon slot 238 in greater detail. Each beaconslot is comprised of a beam settling period 242, the unique wordsequence 244 and a portion of the PN sequence 246. The unique wordsequence is the same in each frame, and helps the beacon demodulator 112recognize that the correct carrier is being acquired and tracked. The PNsequence consists of a plurality of unique PN codes. A typical sequencemay consist of 256 unique PN codes. One PN code is inserted into thebeacon slot of each frame, such that the PN sequence 246 is unique ineach frame 236 of a particular superframe 240. The series of PNsequences 246 repeats in each superframe such that the PN sequenceidentifies the position of each frame within the superframe. Thus, thePN sequence represents the phase of the incoming downlink signal withrespect to the superframe, and repeats every 768 msec. Of course thoseskilled in the art will recognize that the beacon slot may be providedin periodic frames, rather than every frame, and the above descriptionmay be modified to reflect such a situation.

[0071]FIG. 15 is a flowchart depicting an example of the overall programflow of the beacon demodulator 112. As shown, the two major portions ofprogram flow are the start-up mode and the tracking mode. When thebeacon demodulator 112 is first switched on at step 248, the beacondemodulator 112 lacks references to both the timing and frequency of theincoming downlink signal. At this point the DRO frequency has anuncertainty range of +/−4 MHz. Each 3 msec downlink frame is tested at adifferent frequency to cover the entire +/−4 MHz uncertainty range atstep 250. Within each 3 msec window the beacon demodulator 112 tests forthe presence of the unique word sequence. The frequencies are tested in200 kHz increments. Thus, the entire +/−4 MHz uncertainty range iscovered in 41 frames, or 123 msec. At the end of the frequencyacquisition step 250 the NCO is set to the frequency at which thehighest unique word correlation value was generated. The unique wordlock confirmation step 252 confirms that the same unique word is foundin successive frames. If the unique word confirmation step 252 fails,the frequency acquisition step 250 is repeated.

[0072] During the initial frequency acquisition and unique word lockconfirmation steps, the entire 3 msec of each downlink frame is testedfor the presence of the unique word. Also, during this period the gainof the AGC 116 is determined based on the peak power received during any½ time slot interval during each frame. If the unique word lockconfirmation step 252 passes, acquisition continues with the initialtime acquisition step 254. After the initial time acquisition 254, theacquisition integrity is tested at step 256. If the acquisitionintegrity test passes, the system begins a PN phase search and aninitial VCR frequency offset reduction at step 258. If at any time theacquisition integrity fails, the frequency acquisition step 250 must berepeated. Otherwise, the system continues to search for the PN phase andto reduce the initial VCO frequency offset.

[0073] Once the PN phase is found and the initial VCO frequency offsethas been reduced below a certain threshold, acquisition is complete andthe system moves to tracking mode. During the PN phase search and theinitial VCO frequency offset reduction the unique word search window isreduced from the full 3 msec to a +/−30 nsec window. Also, the gain ofthe AGC 116 is determined by unique word correlation value. During thetracking mode, the beacon demodulator performs DLL tracking functions260 and continues to tests the tracking integrity at step 262. Thesystem continues this loop until the tracking integrity test fails. Ifthe tracking integrity test fails, the system goes back to theacquisition integrity test and if the acquisition integrity test fails,the system goes back to the frequency acquisition test 250.

[0074] The steps performed during acquisition mode are described morefully in FIG. 16. The first step is frequency acquisition and UW lockconfirmation 264. During this step, an acquisition flag, flag_aq, is setonce the frequency and unique word lock confirmation has been completed.This process is described in more detail below. The acquisition flag istested at step 266, and if it has not been set, then the frequency ofthe NCO is adjusted at step 268 and the frequency acquisition and uniquelock confirmation step 264 continues. If the acquisition flag has beenset, however, the beacon demodulator 110 begins two parallel processes.The first process consists of an initial timing acquisition step 270, acoarse VCO frequency pull-up step 272 and an adjust VCO step 274. Thesecond parallel process consists of a generate local PN sequence step276, a DRO frequency offset estimator and lock detector step 278 and anadjust NCO frequency step 280. During the two parallel processes, apull-up flag, flag_pull and a lock detection flag, flag_lock , areeither set or not set depending on whether the VCO frequency has beenpulled up to within tolerance and whether the system has locked onto thePN sequence. The mode selection control block 142 tests the lockdetection flag and the pull-up flag at step 282. Once both flags havebeen set, the system moves to the tracking mode. If either the lockdetection flag or the pull-up flag are not set then the system continuesin the acquisition mode.

[0075] The frequency acquisition and unique word lock confirmation step264 discussed above is shown in greater detail in FIG. 17. The firsttask within step 264 is to perform the frequency acquisition functions284. The frequency acquisition functions will be described in greaterdetail below. The system then tests whether the frequency search iscomplete at step 286. If the search is complete, the frequencyacquisition flag (flag_fr_aq) is set to the value 1 at step 288. If thefrequency search is not complete, then the frequency acquisition flag isset to zero at step 290. Next the acquisition flag (flag_aq) is set tozero at step 292 and finally the reset signal is set to zero at step294.

[0076] In parallel with the frequency acquisition functions 284, thefrequency acquisition flag is tested at step 296. If the frequencyacquisition flag has been set, then the time acquisition functions areperformed at step 298. The time acquisition functions will be describedin greater detail below. If the frequency acquisition flag has not beenset, the program flow continues to step 292. After the time acquisitionfunctions 298, the system tests whether a reset is needed at step 300.If a reset is needed, then step 302 is performed in which the frequencyacquisition flag (flag_fr_aq) and the acquisition flag (flag_aq) are setto zero and the reset signal is set to one. If a reset was not needed atstep 300, then the system tests for UW lock at step 302. If the UW locktest passes, then the acquisition flag (flag_aq) is set to one at step306 and then the reset signal is set to zero at step 294. If however,the UW lock test fails, then program flow continues to step 292 in whichthe acquisition flag (flag_aq) is set to zero, then the reset signal isset to zero before continuing.

[0077] Now the frequency acquisition functions identified in step 284 ofFIG. 17 will be described in greater detail as shown in FIG. 18. Thefrequency acquisition functions 284 are performed in the frequencysearch control block 166. First, at step 308 the reset signal is tested.If the reset signal has been set then local variable acquisition count(aq_cnt) is set to zero at step 310. If the reset signal has not beenset, then the acquisition count local variable is not set to zero.Either way, the next step 312 is to test whether the acquisition countvariable is greater than an acquisition stop local variable (aq_stop).If acquisition count is greater than acquisition stop, then program flowcontinues to step 314 in which the two bit frequency control parameter(Fr_control) is set to 10 and the frequency search parameter (Fr_search)is set to 1 before continuing. If the acquisition count is not greaterthan the acquisition stop value, then the next value of c_max isreceived from the time estimation block 158 at step 316. At step 318 thevalue of c_max is tested to see if it is greater of the value ofc_max_buf. If c_max is greater than c_max_buf, then at step 320 thevalue of c_max_buf is updated to be equal to the current value of c_max.Thus, c_max_buf always holds the greatest value of c_max that has beenreceived. Next, at step 322 the variable n max is made equal to thevalue the acquisition count variable (aq_cnt). If c_max was not greaterthan c_max_buf, then steps 320 and 322 are skipped.

[0078] At step 324 the acquisition count variable (aq_cnt) is tested tosee if it is less than the value of the acquisition stop variable(aq_stop). If acquisition count is less than acquisition stop, then instep 326 the frequency control parameter (Fr_control) is set to 00 andthe frequency search parameter is set to 0. If, however, at step 324acquisition count is not less than acquisition stop (acquisition countis equal to acquisition stop), then at step 328 the frequency controlparameter is set equal to 01 and the frequency search parameter is setequal to 1. In either case, after step 326 or 328 the acquisition countvariable is incremented at step 330. After acquisition count isincremented, program flow loops back to step 308.

[0079] The variable acquisition stop is set equal to the number offrequencies to be tested. As described earlier, in the preferredembodiment 41 frequencies are tested to cover the DRO frequencyuncertainty range of +/−4 MHz in 200 kHz increments. Since the variablec_max is the greatest correlation value at each frequency, the variablec_max_buf holds a global maximum correlation value representing thehighest correlation out of all the frequencies tested. N_max then willbe equal to an index to the frequency at which the greatest correlationvalue occurred. The parameter frequency search (Fr_search), is used asan input to the acquisition control state machine 168. Frequency control(Fr_control), is a two bit parameter used by the frequency estimationblock 162. The frequency estimation block 162 in turn uses the frequencycontrol parameter to determine the value of the NCO frequency offset,f_(NCO1). The following Table 2 shows how the frequency controlparameter is interpreted by the frequency estimation block 162. TABLE 2Frequency Control Parameter Interpretation. Fr_Control Interpretation 00Set frequency adjustment f_(NCO1) = Fr_step (constant) 01 Set frequencyadjustment f_(NCOL) = Fr_est (needs to be estimated) 10 Set frequencyadjustment f_(NCO1) = 0 11 Not used

[0080] The timing acquisition functions of step 298 are performed withinthe time search control block 170 shown in FIG. 5. As described above,the three functional blocks within the time search control block 170 arethe threshold control block 172, the search window control block 174,and the false UW lock control block 176. The processes performed by eachof these blocks will now be described.

[0081] The process performed within the threshold control block 172 isshown in FIG. 19. At step 332, the threshold control block 172 receivesthe value of c_max from the time estimation block 158. Next, at step334, the value of c_max is compared against an acquisition thresholdvalue (Th_(aq)) and if c_max is less than the acquisition threshold thanat step 336 the threshold fail control signal (Th_fail) is set equal toone. If c_max is greater than the acquisition threshold, then thethreshold fail control signal set equal to 0 at step 338. The thresholdfail control signal is used by the acquisition control state machine168.

[0082]FIG. 20 illustrates the functionality of the false UW lock controlblock 176. This block protects against the system locking onto the wrongunique word. A local variable (loop_max) is set equal to a maximumnumber of PN code phases to be tested before a failure is detected. Inthis case it is equal to 270, the number of PN phase codes persuperframe (256) plus 14 extra. Loop_max is set equal to 270 at step340. At step 342, the reset signal is tested. If a reset is detected,then the variable loop_count is reset to 0 at step 344. Next, at step346, loop_count is compared to the variable loop_max and if loop_countexceeds loop_max then the false lock control signal (false_lock) is setequal to one at step 348. If however, loop_count remains less thenloop_max, then false_lock is set equal to 0 and the loop_count variableis incremented at step 350. Under ordinary circumstances, loop_countshould never exceed loop_max because the PN phase will be found within256 downlink frames.

[0083] The functionality of the search window control block 174 isdescribed further in FIG. 21. At step 352, a local variable (loop_max)is set equal to 10. At step 354 the reset signal is tested. If the resetsignal is set, then at step 356, the variables flag, pass_old, init andloop_cnt are all set to 0. Next, at step 358 the variable flag istested. If flag is equal to one, then at step 360 the search flag(flag_search) is also set to one and program flow continues. If however,flag is equal to zero at step 258, then at step 362 the variableloop_cnt is incremented and then at step 364 the variable loop_cnt iscompared to loop_max. If loop_cnt is greater than loop_max then thevariable false_lock is set equal to one at step 366, and at step 360flag_search will be set equal to zero. If however, at step 364 loop_cntis not greater than loom_max then program flow continues to step 368, inwhich the variable false_lock is set equal to zero.

[0084] Next, at step 370 the variable init is tested. If init is equalto 0, then at step 372 init is set equal to one, after which programflow loops back to step 354. If however, init was not equal to zero,then program flow continues down to step 374. At step 374 the incomingunique word delta (D_(UW)), received from the course VCO frequencypull-up block 152 is tested against a delta threshold (T_(D)). If theabsolute value of the unique word delta is not less then the deltathreshold, then program flow continues to step 376 in which variablepass_old is set equal to zero and then program flow continues up to step354. If however, in step 374 the unique word delta was less than thedelta threshold, then program flow continues down to step 378 in whichthe variable pass_old is tested. If the variable pass_old is not equalto one, then program flow continues to step 380 in which pass_old is setto one and then program flow loops back to step 354. If however,pass_old was equal to one in step 378, then program flow continues downto step 382 in which the variable flag is set to one, then program flowloops back up to step 354. This portion of the program flow essentiallydetermines when the beacon demodulator has successfully lowered thefrequency offset so that the unique word is received within anacceptable window in two successive frames. In order for the flag to beset equal one, the unique word delta less than delta threshold has to bereceived in successive frames. The variable false_lock is used by theacquisition control state machine 168 and the variable flag_search ispassed back to the UW correlator 156.

[0085] Coarse VCO Frequency Pull-up step 272 of FIG. 16 is shown ingreater detail in FIG. 22. The first step 384 is to test the status of alocal flag (Flag_init) that is set once the coarse VCO frequency pull-upprocedure has been initialized. If Flag_init is equal to zero, than thepull-up procedure has not been initialized, and the process continues atstep 386, coarse VCO frequency pull-up initialization. Next, at step388, the pull-up flag (FLAG_pull) is set to zero, indicating that thepull-up procedure is not complete. Also at step 388, Flag_init is set to1, indicating that the coarse VCO frequency pull-up initializationprocedure has been completed (Flag_init is set to zero whenever a resetsignal is received). Next, the VCO frequency adjustment is computed instep 390.

[0086] If the initialization flag (Flag_init) is set to 1 when coarseVCO frequency pull-up step 272 is begun, program flow continues withstep 392, the coarse VCO frequency pull-up computations. Step 394determines if the coarse VCO pull-up is completed. If it is complete,than FLAG_pull is set to 1 at step 396. If coarse VCO pull-up is notcompleted, than FLAG_pull is set to zero at step 398. Either way,program flow continues with the computation of the VCO frequencyadjustment 390.

[0087] The coarse VCO frequency pull-up computations 392 will now bedescribed more fully. As illustrated in FIGS. 23 and 24, a timedifference (D_(UW)) is calculated between the expected start of theunique word (t′_(UW)), and the actual start of the unique word (t_(UW)).The expected start of the unique word is calculated based on the currentVCO frequency. The actual start of the unique word is received from thetime estimation block 158. If the absolute value of the time difference(D_(UW)) is less than some threshold (T_(D)), which may be, forinstance, ⅙ of a symbol time, than the pull-up procedure has completed,and FLAG_pull is set to 1.

[0088] At step 390, the VCO frequency adjustment is calculated. IfFlag_aq is equal to 1, then the VCO frequency adjustment (f_(VCO)) ismade equal to −D_(UW)/T_(frame), where T_(frame) is equal to the frameduration of 3 msec. If, however, Flag_aq=0, then the VCO frequencyadjustment, f_(VCO) is made equal to zero as well. This is because whenFlag_aq=0, the NCO frequency has not yet been determined.

[0089] The functionality of the PN Sequence Generator 146 is describedmore fully in the flow chart of FIG. 25. The PN Sequence Generatorgenerates the local PN sequence which is used by the tracking block 138and the DRO Frequency Offset Estimator and Lock Detector 134. The PNSequence Generator 146 generates an on-time version of the PN sequencewhich is used by the DRO Frequency Offset Estimator and Lock Detector134 in step 278 shown in FIG. 16. Early and late versions of the PNsequence are also generated by the PN Sequence Generator 146, and usedby the tracking block 138. The PN Sequence Generator 146 operates in oneof two modes, determined by the status of the code flag (FLAG_code)produced by the Mode Selection Control block 140. As shown in FIG. 25,the first step 400 is to test the status of the code flag (FLAG_code).If FLAG_code is equal to zero, then the PN Sequence Generator 146operates in PN Search Mode 402. If FLAG_code is equal to one, then thePN Sequence Generator 146 operates in Regular Mode 404.

[0090] In PN Search Mode 402, the generator's shift registers are loadedwith the set of initial values representing the first of 256 unique PNcodes. The shift registers are loaded once per incoming frame in SearchMode 402. The PN Sequence Generator produces the same PN code each frameas long as the generator 146 is in Search Mode 402. In Regular Mode 404,the generator shift registers are loaded with the initial set of values.The generator then generates all 256 PN codes, and is reloaded with theinitial set of values once every 256 frames. Thus, in regular mode 404,the generator produces 256 PN codes and delivers one code per frame for256 frames. At step 406 the generator 146 generates the PN sequence. Thegenerator 146 initially receives the PN starting time (t_(PN)) from thetime estimation block 158. Once the beacon demodulator is in trackingmode, the generator 146 calculates the starting time from the VCO clock122. In tracking mode, a new PN code is produced every 3 msec worth ofVCO clock ticks. At step 408, the on time PN sequence is advanced anddelayed by ½ PN symbol time in order to generate the early and late PNsequences. The outputs of the PN Sequence Generator 146 are the on-time,early, and late PN sequences.

[0091] The DRO Frequency Offset Estimator and Lock Detector step 278 ofFIG. 16 is shown in greater detail in FIG. 26. During the first step 410the DRO offset frequency is estimated within the DRO Frequency OffsetEstimator and Lock Detector block 134. At step 412, if the lock detector232 determined that the system is locked onto the incoming PN sequence,then the lock flag (FLAG_lock) is set equal to one at step 414.Otherwise, if the system is not locked, then the lock flag is set tozero at step 416. The lock flag (FLAG_lock) is sent from DRO FrequencyEstimator and Lock Detector block 134 to Mode Selection Control block140. The lock flag is also used internally within block 134, being sentfrom Lock Detector block 232 to Frequency Estimator block 234.

[0092] Once the acquisition mode is completed and the conditionsnecessary for tracking mode have been met (Coarse VCO frequency pull-upis complete and lock detector 232 detects lock), the system switched totracking mode. The program flow of tracking mode is show in FIG. 27.Tracking mode is similar to acquisition mode in that the VCO pull up andDRO frequency offset processes happen in parallel. Incoming samplescontinue to be received at both the tracking block 138 and the DROFrequency Offset Estimator and Lock Detector 134. On-time, early andlate PN sequences are generated at step 418 (in PN Sequence Generator146). The incoming samples and on-time PN sequence are received by theDRO Frequency Offset Estimator and Lock Detector 134. At step 420, theDRO frequency offset is calculated. If lock is detected 422, then thelock flag is set to one at step 424. If lock is not detected, then thelock flag is set to zero 426. Finally, the NCO frequency is adjusted atstep 428.

[0093] At the same time, incoming samples and the early and late PNsequences are delivered to the discriminate function block 186. TheDiscriminate Function Computations occur at step 430. The discriminatefunctions were described above and in FIGS. 7 and 8. At step 432 thetracking control block 184 determines if fine VCO pull-up has beencompleted. If it has, then the 3^(rd) order DLL loop filter 192 isenabled at step 434. Otherwise, a simple gain loop 190 is enabled atstep 436. At step 438 the VCO frequency is adjusted. Finally, at step440, the status of the lock flag (FLAG_lock) is tested. If the lock flagis still set, then the mode flag (FLAG_mode) continues to be set, thesystem remains in tracking mode and the next frame of samples areprocessed. If, however, the lock flag (FLAG_lock) was set to zero,indicating that the system is no longer locked onto the incoming PNsequence, then the system returns to the acquisition mode.

[0094] Although only a few exemplary embodiments of this invention havebeen described in detail above, those skilled in the art will readilyappreciate that many modifications are possible in the exemplaryembodiments without materially departing from the novel teachings andadvantages of this invention. Accordingly, all such modifications areintended to be included in the scope of this invention as defined in thefollowing claims.

What is claimed is:
 1. A method of providing a synchronization signal toa terminal which is adapted for use in a communications network, themethod comprising: transmitting to said terminal a communication signalcomprising a plurality of frames, each of said frames comprising atleast one time slot; and including a respective portion of saidsynchronization signal in at least one said time slot of a plurality ofsaid frames, said synchronization signal including data which is adaptedfor use by said terminal to control transmission timing of saidterminal.
 2. The method of claim 1 wherein said including step includesin each of said frames said respective portion of said synchronizationsignal in at least one time slot.
 3. The method of claim 1, wherein saidincluding step includes said portion of said synchronization signal ineach said frame, such that said synchronization signal comprises aunique word signal that is substantially the same in each frame.
 4. Themethod of claim 1, wherein: said transmitting step further includesaranging respective groups of said frame into respective superframe, andfor each said superframe, said including step includes a portion of saidsynchronization signal in each said frame, such that each said portioncomprises a respective phase signal that is unique for each respectiveframe within a particular superframe.
 5. The method of claim 4, whereinsaid transmitting step further includes transmitting the start of eachof said superframe such that it substantially coincides with the startof one of said frames.
 6. The method of claim 5 wherein saidtransmitting step further includes transmitting the start of each ofsaid frames such that it substantially coincides with the start of oneof said time slots.
 7. The method of claim 4, wherein said includingstep includes said phase signals in said frames of said superframes inthe same order for each said superframe.
 8. A method of determining thepower level of a communications signal comprising a plurality of timeslots, the method comprising: measuring the power of the communicationssignal in substantially continuous discrete time periods, each timeperiod being less than the duration of one of said time slots, settingthe gain of an automatic gain control circuit based on the maximum powerin any time period; and controlling said automatic gain control circuitto apply said gain to said communications signal.
 9. The method of claim8, wherein said measuring step uses said time periods that are each nomore than half of the duration of one of said time slots.
 10. A methodof acquiring a signal being transmitted within a range of possiblefrequencies at a terminal adapted for use in a satellite communicationsystem, the method comprising: receiving said signal at said terminal,said signal comprising a plurality of frames, a portion each framecomprising a unique word pattern; testing at least one of a plurality ofpossible frequencies within said range for the duration of at least oneframe for the presence of the unique word pattern; and repeating saidtesting step at additional respective frequencies within said rangeuntil said unique word pattern is detected.
 11. The method of claim 10wherein said testing step further includes: determining a correlationvalue for each tested frequency; and said repeating step furtherincludes detecting said unique word pattern when the correlation valueis above a threshold value.
 12. The method of claim 10 wherein saidtesting step further includes: determining a correlation value for eachof said plurality of possible frequencies, and identifying a maximumcorrelation value from the plurality of correlation values.
 13. Themethod of claim 12 further comprising determining a transmissionfrequency based on the frequency associated with said maximumcorrelation value.
 14. A method of providing a synchronization signal toa terminal adapted for use in a satellite communication system, themethod comprising: generating said synchronization signal as a pluralityof unique phase signals; and transmitting a communication signal to saidterminal, said communication signal comprising a plurality of frames, aportion of each frame comprising a respective one of said plurality ofunique phase signals.
 15. The method of claim 14 wherein saidcommunication signal comprises a plurality of superframes, eachsuperframe comprising a plurality of said frames, such that the order ofunique phase signals in each frame repeats in every superframe.
 16. Themethod of claim 15 wherein the number of frames per superframe is equalto the number of unique phase signals.
 17. The method of claim 15,wherein said transmitting step transmits said communication signal suchthat the beginning of each superframe substantially coincides with thebeginning of one of said frames.
 18. A method of determining the phaseof a satellite communications signal comprising a plurality of frames,and having a series of unique phase signal time division multiplexedinto at least one time slot of each respective frame, a plurality offrames forming a superframe such that the order of said unique phasesignals repeats in each superframe, the method comprising: correlatingthe phase signal portion of each frame with a reference phase signal;generating a correlation value for each frame; and determining the startof the superframe based on the frame generating the highest correlationvalue.
 19. The method of claim 18, wherein said unique phase signalscomprise pseudonoise sequences.
 20. The method of claim 18, wherein saidreference phase signal comprises a pseudonoise sequence substantiallyidentical to one of the series of unique phase signals.
 21. The methodof claim 18, wherein said reference phase signal is substantiallyidentical to the first unique phase signal in each superframe.
 22. Amethod of acquiring a communication signal, the communication signalcomprising a plurality of frames, each frame comprising a plurality oftime slots, at least one time slot in each frame having synchronizationdata with a unique word signal contained therein, the method comprising:(a) setting the gain of an automatic gain control circuit based on themaximum power measured in continuous time intervals being less than theduration of one time slot of each frame; (b) correlating at least oneframe with a locally generated unique word signal at at least one of aplurality of possible frequencies; (c) storing a correlation value foreach of said possible frequencies; (d) setting a numerically controlledoscillator (NCO) frequency based on a desired correlation value of saidpossible frequencies; (e) repeating steps (a)-(d) while the correlationvalue is below a frequency acquisition threshold, and when saidcorrelation value is at least equal to said frequency acquisitionthreshold, performing the steps of: (f) determining an arrival time ofthe unique word signal in a first frame; (g) estimating an estimatedarrival time of the unique word signal in a second frame based on thearrival time of the unique word signal in said first frame; (h)determining the actual arrival time of the unique word signal in saidsecond frame; (e) calculating a difference between the estimated arrivaltime and the actual arrival time; (j) adjusting a voltage controlledoscillator (VCO) frequency based on said difference; (k) repeating steps(f)-(j) while said difference is not below a timing acquisitionthreshold to determine acquisition of said communication signal.
 23. Themethod of claim 22, wherein said step of setting the gain measures timeintervals that are no more than half of the duration of one time slot.24. The method of claim 22 wherein said correlating step is performed ateach of said plurality of possible frequencies.
 25. The method of claim22 wherein said step of setting the NCO frequency sets the NCO frequencybased on the maximum correlation value of said possible frequencies. 26.A system for providing a synchronization signal to a terminal which isadapted for use in a communications network, the system comprising: atransmitter for transmitting to said terminal a signal including aplurality of frames, each of said frames including at least one timeslot; wherein said transmitter includes a respective portion of saidsynchronization signal in at least one said time slot of a plurality ofsaid frames, said synchronization signal including data which is adaptedfor use by said terminal to control the transmission timing of saidterminal.
 27. The system of claim 26 wherein each of said framesincludes a respective portion of said synchronization signal in at leastone time slot.
 28. The system of claim 26, wherein said synchronizationsignal includes frequency data which is further adapted for use by saidterminal to control transmission frequency of said terminal; and saidsystem controls said transmission frequency based on said frequencydata.
 29. The system of claim 26, wherein the portion of saidsynchronization signal in each said frame includes a unique word signalthat is substantially the same in each frame.
 30. The system of claim26, wherein the signal includes a plurality of superframes, each of saidsuperframes including a plurality of said frames, and wherein saidportion of said synchronization signal includes a phase signal that isunique for each frame within a particular superframe.
 31. The system ofclaim 30, wherein the start of each of said superframes substantiallycoincides with the start of one of said frames.
 32. The system of claim31, wherein the start of each of said frames substantially coincideswith the start of one of said time slots.
 33. The system of claim 30,wherein said transmitter includes said phase signals in said frames suchthat the order of the phase signals is the same in each respectivesuperframe.
 34. A system for determining the power level of acommunication signal comprising a plurality of time slots, the systemcomprising: a power measuring circuit adapted to measure the power ofthe communication signal in substantially continuous discrete timeperiods, each time period being less than the duration of one of saidtime slots, and a gain setting device adapted to set the gain of anautomatic gain control circuit based on the maximum power in any timeperiod, and to apply said gain to said communication signal.
 35. Thesystem of claim 34, wherein each of said time periods is no more thanhalf of the duration of one of said time slots.
 36. A system foracquiring a signal being transmitted within a range of possiblefrequencies at a terminal adapted for use in a satellite communicationsystem, the system comprising: a receiver adapted to receive said signalat said terminal, said signal comprising a plurality of frames, aportion each frame comprising a unique word pattern; and a testingdevice adapted to test at least one of a plurality of possiblefrequencies within said range for the duration of at least one frame forthe presence of the unique word pattern and for repeating said test atadditional respective possible frequencies until said unique wordpattern is detected.
 37. The system of claim 36 wherein the testingdevice is adapted to determine a correlation value for the testedfrequency, and the unique word pattern is detected when the correlationvalue is above a threshold value.
 38. The system of claim 36, whereinsaid testing device is further adapted to determine a correlation valuefor each of said plurality of possible frequencies, and to identify amaximum correlation value from the plurality of correlation values. 39.The system of claim 38 wherein said testing device is further adapted toset transmission frequency based on the frequency associated with saidmaximum correlation value.
 40. A system for providing a synchronizationsignal to a terminal adapted for use in a satellite communicationsystem, the system comprising: a transmitter adapted to generate saidsynchronization signal as a plurality of unique phase signals and totransmit said synchronization signal to said terminal, saidsynchronization signal comprising a plurality of frames, a portion ofeach frame comprising a unique one of said plurality of unique phasesignals.
 41. The system of claim 40, wherein the synchronization signalcomprises a plurality of superframes, each superframe comprising aplurality of said frames, such that the order of unique phase signals ineach frame repeats in each superframe.
 42. The system of claim 41wherein the number of frames per superframe is equal to the number ofunique phase signals.
 43. The system of claim 41, wherein the beginningof each superframe coincides with the beginning of one of the frames.44. A system for determining the phase of a satellite communicationssignal comprising a plurality of frames, and having a series of uniquephase signals time division multiplexed into at least one time slot ofeach respective frame, a plurality of frames forming a superframe suchthat the unique phase signals repeat in each superframe, the systemcomprising: a correlation device adapted to correlate the phase signalportion of each frame with a reference phase signal; generate acorrelation value for each frame; and determine the start of thesuperframe based on the frame generating the highest correlation value.45. The system of claim 44, wherein the unique phase signals comprisepseudonoise sequences.
 46. The system of claim 44, wherein the referencephase signal comprises a pseudonoise sequence substantially identical toone of the series of unique phase signals.
 47. The system of claim 46,wherein the reference phase signal is substantially identical to thefirst unique phase signal in each superframe.
 48. A system for acquiringa communication signal, the communication signal comprising a pluralityof frames, each frame comprising a plurality of time slots, at least onetime slot in each frame having synchronization data with a unique wordsignal contained therein, the system comprising: a correlator adapted tocorrelate at least one frame of said communication signal with a locallygenerated unique word signal at at least one of a plurality of possiblefrequencies, to store a correlation value for each of said possiblefrequencies, and to set a numerically controlled oscillator (NCO)frequency based on a desired correlation value of said possiblefrequencies; a gain setting device adapted to set the gain of anautomatic gain control circuit (AGC) based on the maximum power measuredin each frame in predetermined time intervals each being less than theduration of one time slot, to apply said gain to said communicationsignal, and to continue setting the gain of the AGC until saidcorrelator generates a correlation value above a frequency acquisitionthreshold; a voltage controlled oscillator (VCO) frequency offsetreducer adapted to: (a) determine an arrival time of the unique wordsignal in a first frame; (b) estimate an estimated arrival time of theunique word signal in a second frame based on the arrival time of theunique word signal in said first frame; (c) determine the actual arrivaltime of the unique word signal in said second frame; (d) calculate adifference between the estimated arrival time and the actual arrivaltime; (e) adjust a VCO frequency based on said difference, and (f)repeat functions (a)-(e) on subsequent frames if said difference is notbelow a timing acquisition threshold value; and a mode selection circuitfor causing the system to enter a tracking mode if said difference isbelow said timing acquisition threshold value.
 49. The system of claim48, wherein said predetermined time interval is no more than half of theduration of one time slot.
 50. The system of claim 48, wherein saidcorrelator correlates at least one frame with a locally generated uniqueword signal at each of said plurality of possible frequencies.
 51. Thesystem of claim 48, wherein the correlator sets the NCO frequency basedon the maximum correlation value of said possible frequencies.